A typical deflection circuit in a television receiver includes an output stage that generates a deflection current in a deflection winding and that generates retrace pulses used for generating an ultor voltage. The output stage is controlled by a horizontal rate switching control signal.
Timing of the deflection current produced by the horizontal deflection circuit output stage may vary in a manner dependent upon loading of the ultor voltage source. For example, such loading may be dependent upon the brightness of the image being displayed on a kinescope of the receiver. Variation in such loading causes, for example, a corresponding variation in a delay of the horizontal retrace pulses and of the deflection current. Furthermore, disadvantageously, it may cause a distortion of the image being displayed.
A circuit embodying the invention includes a dual feedback loop arrangement that is used for preventing the occurrence of the variation in the delay of the deflection current relative to, for example, a horizontal synchronizing signal. In such arrangement, a horizontal oscillator generates a signal at, for example, a frequency greater than the horizontal frequency. The oscillator generated signal is divided down in a frequency divider and a first output signal that is at or near the horizontal frequency is generated. The oscillator, frequency divider and a first phase detector are included in a phase-lock-loop circuit (PLL) that is synchronized by the horizontal synchronizing signal that is obtained, for example, from a sync separator of the television receiver.
The PLL, having a relatively long time constant, controls the oscillator to maintain the first output signal in frequency and phase synchronism with the horizontal synchronizing signal.
In order to compensate for such load dependent variations in the delay associated with the horizontal deflection circuit output stage, a phase-control-loop circuit (PCL) is used. The PCL includes a second phase detector, a first input terminal of which is coupled to the first output signal of the PLL and a second input terminal of which is coupled to the deflection circuit output stage for responding to the retrace pulse generated by the output stage. The phase detector produces a phase difference indicative signal from the signals at the first and second input terminals. A low-pass, loop filter generates a control signal from the phase difference indicative signal. A phase shifting arrangement that is responsive to the control signal produces a horizontal-rate output signal having pulses at the horizontal rate and at a variable delay which makes, for example, the retrace pulses synchronous with the horizontal synchronizing signal even when variations of beam current loading occur.
The PLL may be internal to an integrated circuit (IC) such as, for example, TA 7777 that is made by Toshiba Co. (the Toshiba IC). The Toshiba IC produces, at corresponding output terminals, the first output signal at the horizontal frequency and the aforementioned second output signal at the frequency that is greater than the horizontal frequency and that is synchronized to the first output signal.
In a typical television display system, the high voltage ultor accelerating potential is applied to the final anode electrode of a picture tube to accelerate an electron beam generated at a picture tube cathode onto a phosphor screen. To ensure that the television receiver will not be operated, under a fault condition, at excessive ultor potential level, a high voltage protection circuit is incorporated in the television receiver circuitry. Thus, for example, the Toshiba IC includes such high voltage protection circuit. An excessive ultor potential level, for example, will disable, in the Toshiba IC, the generation of the horizontal rate first output signal, but not of the second output signal at the frequency that is greater than the horizontal frequency.
The PCL that, in a circuit embodying the invention, may be internal to a second IC, is constructed in such a way that it utilizes the second output signal of the PLL of the Toshiba IC that is at the frequency that is greater than the horizontal frequency for its internal operation. Utilization of the second output signal, advantageously, simplifies the design of the PCL. The output signal of the PCL that is synchronized to the first output signal of the PLL controls the switching timing in the deflection circuit output stage.
When the Toshiba IC is used to provide the PLL operation that was described before, the output signal of the PCL may be generated as a result of the presence of the second output signal at the greater frequency even when the first output signal, as a result of the fault condition, is disabled. Disadvantageously, the fault protection circuit of the Toshiba IC, by itself, will not prevent the generation of the output signal of the PCL and, hence, will not prevent the generation of the ultor voltage.
In accordance with an aspect of the invention, recurring signal transitions in the first output signal are detected. When no recurring signal transitions occur, that is indicative of the fault condition, a detection circuitry that detects such signal transitions disables the generation of the output signal of the PCL and thereby prevents the generation of the ultor voltage.